1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device, and more specifically, to a data programming system of a NAND type flash EEPROM, for example.
2. Description of the Related Art
As a nonvolatile semiconductor memory device which can be electrically rewritten and formed with high integration density, a NAND type flash EEPROM is well known in the art. A memory transistor in the NAND type flash EEPROM has a stacked gate structure in which a charge storage layer (floating gate) and control gate are stacked and formed above a semiconductor substrate with an insulating film disposed therebetween. A NAND cell unit is configured by serially connecting a plurality of memory transistors in a column direction while adjacent ones of the memory transistors commonly have a source or drain and connecting selection gate transistors to both ends of the series-connected memory transistor circuit.
A memory cell array is configured by arranging a plurality of NAND cell units with the above-described structure in a matrix form. In this case, a group of NAND cell units arranged in a row direction is called a NAND cell block. The gates of selection gate transistors arranged on the same row are commonly connected to a corresponding one of selection gate lines and the control gates of memory transistors arranged on the same row are commonly connected to a corresponding one of control gate lines. If n memory transistors are serially connected in the NAND cell unit, the number of control gate lines contained in one NAND cell block is n.
The memory transistor stores data in a nonvolatile fashion according to the charge storage state of the floating gate. More specifically, the memory transistor stores binary data on the assumption that a state in which electrons are injected from the channel into the floating gate to set the threshold voltage high is defined as “0” data and a state in which electrons in the floating gate are discharged into the channel to set the threshold voltage low is defined as “1” data. Recently, a multi-value data storage process such as a four-value data storage process is performed by more finely dividing the distribution of the threshold voltage.
When programming data, first, data items in the NAND cell block are simultaneously erased in advance. The erase process is performed by setting all of the control gate lines (word lines) of a selected NAND cell block to low voltage Vss (for example, 0V) and applying high positive voltage Vera (erase voltage, for example, 20V) to a p-type well region in which the memory cell array is formed to discharge electrons in the floating gates into the channel regions. As a result, data items in the NAND cell block are all set to “1” data. The unit of data to be simultaneously erased is not limited to a NAND cell block unit and can be set to a whole chip unit, for example.
The data programming process is simultaneously performed for a plurality of memory transistors connected to a selected control gate line after the above-described simultaneous data erase process. The unit of data to be programmed is generally defined as one page. In recent years, a plurality of pages are allocated for one control gate line in some cases. The order in which data is programmed into the memory transistors in the NAND cell block is determined based on a system in which data is programmed in a random order (random programming process) and a system in which data is sequentially programmed in one direction (sequential programming process). In the sequential programming process, generally, data is programmed in order from the source-side memory transistor.
If high positive voltage Vpgm (program voltage, for example, 20V) is applied to a selected control gate line in the simultaneous programming process, electrons are injected from the channel of the memory transistor into the floating gate in the case of “0” data (so-called “0” programming or “0” write). In this case, injection of electrons is inhibited in the case of “1” data (so-called program inhibition, “1” programming or “1” write). Thus, two types of data programming operations are simultaneously performed. In order to realize the above simultaneous programming process, it is necessary to control the channel voltage of the memory transistor according to program data. For example, in the case of “0” data, the channel voltage is kept low so as to apply a strong electric field to the gate insulating film under the floating gate when the program voltage Vpgm is applied to the control gate. In the case of “1” data, the channel voltage is boosted so as to make weak the electric field applied to the gate insulating film and inhibit injection of electrons into the floating gate. At this time, if the channel voltage is insufficiently boosted, electrons are injected so that the threshold voltage of the memory transistor to be subjected to the “1” programming process will be changed. The phenomenon is hereinafter referred as “erroneous programming” or “write error”. Therefore, in order to realize the programming operation of the NAND type flash EEPROM, it is necessary to suppress a variation in the threshold voltage due to erroneous programming within a specified range so as not to cause the erroneous operation.
Various types of channel voltage control methods at the programming time are provided. Among them, the self-boost (SB) programming method for setting all of the channel regions of the NAND cell unit into an electrically floating state in the “1” data programming case and boosting the channel voltage by use of capacitive coupling with the control gate is most popularly used. The self-boost programming method is described in K. D. Suh et. al., IEEE Journal of Solid-State Circuits, vol. 30, No. 11 (1995) pp. 1149–1156, for example.
Next, the SB method is more specifically explained with reference to FIG. 1A. Before applying program voltage to the control gate line, bit line voltages Vbl1, Vbl2 are applied to bit lines BL1, BL2 according to “0” data, “1” data. For example, as Vbl1, 0V is used, and as Vbl2, a voltage of 1.2V to 4.0V is used, for example. Selection gate transistors SG1,1, SG1,2, . . . on the bit line side are required to be turned ON in order to transfer the bit line voltage Vbl1 in the NAND cell unit in which “0” data is programmed. Also, in this case, the selection gate transistors on the bit line side are automatically set into the cut-off state at the channel voltage boosting time in the NAND cell unit in which “1” data is programmed. That is, gate voltage Vsgd which satisfies a condition of Vth—sgd(0)<Vsgd<Vbl2+Vth—sgd(Vbl2) is applied to the selection gate line on the bit line side. In this case, Vth—sgd indicates the threshold voltage of the selection gate transistor on the bit line side and the symbols in the parentheses indicate back bias voltage applied to the source of the selection gate transistor on the bit line side. Generally, as the voltage Vsgd, the same voltage (in this case, Vbl2) as the bit line voltage in the case of “1” data programming is given in many cases. Voltage Vsgs (for example, 0V) which sets selection gate transistors SG2,1, SG2,2, . . . on the source side into the cut-off state is applied to the selection gate line on the source side. After this, program voltage Vpgm is applied to the selected control gate line used for programming and intermediate voltage Vpass (for example, 10V) which is lower than Vpgm is applied to the other non-selected control gate lines. In the NAND cell unit in which a “0” data programming process is performed, the channel voltage is fixed at Vbl1 and a strong electric field is applied to the gate insulating film of the selected memory transistor so as to inject electrons into the floating gate by the tunnel effect. In the case of “1” programming, the selection gate transistors on both ends of the NAND cell unit are turned OFF to electrically isolate the memory transistors as shown in FIG. 1B. Therefore, the channels and diffusion layers of all of the memory transistors are set into the electrically floating state while they are serially connected. As a result, the voltage of the channel and diffusion layer is boosted to certain channel voltage Vch by use of capacitive coupling with the control gate line to make weak the electric field applied to the gate insulating film and suppress injection of electrons into the floating gate.
The channel voltage Vch at the self-boosting time is expressed by the following series of equations.Vch=Vch—init+Cr1·(Vpass-Vthbk-Vch—init)+Cr2·(Vpgm-Vth-Vch—init)  (1)Vch—init=Vsgd-Vth—sgd  (2)Ct=n·Cch+n·Cins  (3)Cr1=(n−1)·Cins/Ct  (4)Cr2=Cins/Ct  (5)where Vch—init indicates an initial value of the channel voltage, Vth the threshold voltage of the selected memory transistor, Vthbk the threshold voltage of the non-selected memory transistor, Cp the coupling ratio of the memory transistor, Cins the capacitance between the control gate and substrate of one memory transistor, Cch the sum of the junction capacitance of the diffusion layer and the depletion capacitance of the channel portion of one memory transistor, Ct the total capacitance connected to the boost region, and n the number of memory transistors contained in the NAND boost region.
When the control gate voltage is gradually raised at the Vpass pulse application time and reaches (Vthbk+Vch—init), the boost region (the channels and diffusion layers of all of the memory transistors in the SB system) is electrically isolated from the selection gate transistors. The initial voltage transferred to the channel until then is Vch—init.
According to the equation (1), the channel voltage Vch is associated with Vpass and Vpgm with the boost ratios Cr1 and Cr2. As indicated by the equations (4), (5), the SB system has a feature that the channel voltage Vch is almost determined by Vpass since Cr2 is as small as 1/(n−1) times Cr1.
As one of the channel voltage control systems other than the self-boost system, a local self-boost system (LSB) as shown in FIGS. 2A and 2B is known. The local self-boost system is described in Jpn. Pat. Appln. KOKAI Publication No. 08-279297, for example. In the above system, a sequential programming method for sequentially programming data starting from the control gate line on the source side as described before is generally used. As shown in FIG. 2B, the system is to set the memory transistors on both sides of the selected memory transistor into the cut-off state, electrically isolate only the channel and diffusion layers (boosted region BA1 in FIG. 2B) of the selected memory transistor from the remaining memory transistors, set the above regions into the electrically floating state and boost the voltage thereof. Thus, the higher channel voltage can be attained in comparison with the case of the SB system. Specifically, program voltage Vpgm is applied to the control gate line of the selected memory transistor and low voltage Vcutoff (for example, 0V) which cuts off the memory transistor is applied to the control gate lines of the memory transistors which are adjacent thereto. Intermediate voltage Vpass between Vpgm and Vcutoff is applied to the other non-selected control gate lines (FIG. 2A). When the equations described before are taken into consideration, the number of memory transistors boosted is “1” in the LSB system (n=1), and therefore, the boost ratio Cr2 becomes equal to Cins/(Cch+Cins) and is larger than in the case of the SB system. In addition, since the boost ratio is multiplied by the program voltage Vpgm, the third item in the equation (1) becomes extremely large (the second item is “0”) and the channel voltage to be reached becomes higher than in the case of the SB system.
As the other channel voltage control system, an erased area self-boost (EASB) system as shown in FIGS. 3A and 3B is proposed. The erased area self-boost system is described in Jpn. Pat. Appln. KOKAI Publication No. 10-283788, for example. The system is based on the sequential programming method for sequentially programming data starting from the control gate line on the source side as described before. As shown in FIG. 3A, low voltage Vcutoff is applied to the control gate line of the memory transistor which lies adjacent to and on the source side of the selected memory transistor so as to cut off the memory transistor. Program voltage Vpgm is applied to the control gate line of the selected memory transistor and intermediate voltage Vpass is applied to the other non-selected control gate lines. In this case, as shown in FIG. 3B, the boosted area is limited to the selected memory transistor and the memory transistors which lie on the bit line side with respect to the selected memory transistor (boosted area BA1 in FIG. 3B). Because of the sequential programming, all of the memory transistors in the boosted area are set in the erased state and the second item in the equation (1) becomes sufficiently large, and therefore, channel voltage which is higher than in the case of the SB system can be obtained.
Even if any type of the channel voltage control system is used, it is definitely necessary to optimize pulse voltages Vpgm, Vpass applied to the control gates of the memory transistors at the programming time in order to attain high resistance to erroneous programming. The program voltage Vpgm is unconditionally determined based on the programming characteristic of the memory transistor. Therefore, the way of determining the intermediate voltage Vpass has an extremely important meaning with respect to the programming characteristic. Generally, the intermediate voltage Vpass is determined by attaining a balance between two types of erroneous programming stresses occurring while data is programmed into the memory transistors connected to all of the control gate lines. The two types of erroneous programming stresses are explained in detail with reference to FIG. 1A by taking the case of the SB system as an example.
The first erroneous programming stress is stress applied to the memory transistor connected to the selected control gate line in the NAND cell unit in which the “1” programming operation is performed (refer to a memory transistor MTA in FIG. 1A). If stress voltage is defined as “a difference between control voltage and channel voltage”, then the stress voltage becomes equal to (Vpgm-Vch). The erroneous programming stress is referred to as “Vpgm stress”. The Vpgm stress occurs only once in one memory transistor which stores “1” data while all of the control gate lines are selected and used for programming.
The second erroneous programming stress is stress applied to the non-selected memory transistor in the NAND cell unit in which the “0” programming operation is performed (refer to a memory transistor MTB in FIG. 1A). In this case, the control gate voltage is Vpass, the channel voltage is Vbl1 (for example, 0V) and the stress voltage is Vpass-Vbl1≈Vpass. The erroneous programming stress is referred to as “Vpass stress”. However, it should be noted that, if the number of control gate lines is “n”, the Vpgm stress applied to one “1” data memory transistor occurs (n−1) times at maximum while all of the control gate lines are selected and used for programming and the “Vpgm stress” is defined by the total sum of the stresses. Therefore, the memory transistor MTB in FIG. 1A expresses a state in which the Vpass stress of one control gate line is applied and a value which is equal to (n−1) times the above Vpass stress is used as the “Vpass stress”.
There occurs a case wherein stress voltage is “Vpass-Vch” as indicated by a memory transistor MTC in FIG. 1A as erroneous programming stress applied to the memory transistor, but the above stress is sufficiently small in comparison with the above two types of stresses and is neglected.
As described above, the “total erroneous programming stress” which the memory transistor undergoes when “1” data is programmed is given as the sum of Vpgm stress and Vpass stress.
The Vpass optimization method is performed as follows. First, as shown in FIG. 4, Vpass is plotted on the abscissa and threshold voltages after application of the two types of erroneous programming stresses are plotted on the ordinate. In the case of the SB system, since the channel voltage Vch becomes higher as the intermediate voltage Vpass becomes higher, the Vpgm stress characteristic generally shows the tendency to move down to the right as indicated by a solid line. On the other hand, the Vpass stress characteristic shows the tendency to move up to the right as indicated by broken lines indicating that the threshold voltage increases in proportion to an increase in Vpass. That is, the curves of the Vpgm stress and Vpass stress show the characteristics which are contrary to each other and have an intersection. In order to minimize both of the stresses, generally, a Vpass value near the intersection (Vpass—optimum in FIG. 4) is used. Further, as the threshold voltage at the intersection (Vth—intersection) is lower, the programming characteristic is better. In this example, the SB system is explained, but the basic tendency is the same in the LSB system and EASB system. However, the Vpass stress characteristic is the same as that in the SB system, but it is considered that the Vpgm stress becomes smaller than that in the SB system, and therefore, the intersection is shifted down to the left (erroneous programming stress decreases).
According to the trend of miniaturization of recent semiconductor integrated circuit devices, the gate length of a memory transistor of the NAND type flash EEPROM will soon become smaller than 0.1 μm. With the further miniaturization, a lowering in the threshold voltage due to the short channel effect becomes more significant. Since a significant lowering in the threshold voltage is not desirable from the viewpoint of reliability, a lowering in the threshold voltage due to the short channel effect is compensated for by enhancing the concentration of impurity used in the channel ion-implantation process. As a result, the Vpass stress can be kept at substantially the same level without depending on scaling. However, since an increase in the channel impurity concentration leads to a reduction in the boost ratio expressed in the equations (4), (5), it lowers the channel voltage Vch and gives rise to an increase in the Vpgm stress. As the result of this, the scaling tends to increase the erroneous programming stress.
Further, as the technique for increasing the memory capacity without scaling, recently, a multi-value storage system is highly expected. However, if the multi-value storage system is used, the threshold voltage range of the memory transistor used for data recording is enlarged, and therefore, it is inevitably necessary to enhance the program voltage Vpgm. Since an increase in the programming voltage makes the Vpgm stress larger, a method for more stably preventing the erroneous programming is required in order to realize the multi-value storage system.
Based on the above trend, it is desired to improve the programming characteristic of the nonvolatile semiconductor memory device.